module ledG_press_IO(
    input   wire            sclk,
    input   wire            input_active,
    input   wire            detect_sync,
    input   wire            sample_sync,
    
    input   wire            inner_led_g,                
    output  wire            led_g
    
    );

reg         detect_input;
reg  [1:0]  sample_period_count;

assign led_g=(detect_input==0)? inner_led_g:1'bz;

always@(posedge sclk)
    if(detect_input==0)
        sample_period_count<=1'b0;
    else if(sample_sync==1 && sample_period_count[1]==0)
        sample_period_count<=sample_period_count+1'b1;

always@(posedge sclk)
    if (input_active==1)
        detect_input<=1'b0;
    else
        begin
        if(detect_sync==1)                
            detect_input<=1'b1;
        else if(sample_sync==1 && sample_period_count[1]==1)
            detect_input<=1'b0;
        end

endmodule
